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zh-tw [2017/11/14 01:27]
takahiro [Current Project]
zh-tw [2017/12/20 01:10] (現在)
takahiro [Current Project]
ライン 21: ライン 21:
 =====Current Project===== =====Current Project=====
   * [[http://​mist32.github.io/​mist32-isa/​|MIST32 : Our original new processor architecture optimized for Out of Order execution]]   * [[http://​mist32.github.io/​mist32-isa/​|MIST32 : Our original new processor architecture optimized for Out of Order execution]]
 +    * [[https://​github.com/​cpulabs/​mist1032sa|MIST1032SA : (MIST32 Type-S) Out of Order execute implemented by Verilog HDL]]
 +    * [[https://​github.com/​cpulabs/​mist1032isa|MIST1032ISA : (MIST32 Type-S) In-order simple implemented by Verilog HDL]]
     * [[https://​github.com/​cpulabs/​mist32e10fa|MIST32E10FA : (MIST32 Type-E) In-order simple implemented by System Verilog]]     * [[https://​github.com/​cpulabs/​mist32e10fa|MIST32E10FA : (MIST32 Type-E) In-order simple implemented by System Verilog]]
     * MIST32E20FA : (MIST32 Type-E) Out of Order execute implemented by System Verilog : coding now.     * MIST32E20FA : (MIST32 Type-E) Out of Order execute implemented by System Verilog : coding now.
-    * [[https://​github.com/​cpulabs/​mist1032sa|MIST1032SA : (MIST32 Type-S) Out of Order execute implemented by System Verilog]] 
-    * [[https://​github.com/​cpulabs/​mist1032isa|MIST1032ISA : (MIST32 Type-S) In-order simple implemented by System Verilog]] 
     * [[https://​github.com/​techno/​gcc-mist32|gcc for MIST32 architecture]] ([[https://​github.com/​techno|hktechno]] coded)     * [[https://​github.com/​techno/​gcc-mist32|gcc for MIST32 architecture]] ([[https://​github.com/​techno|hktechno]] coded)
     * [[https://​github.com/​techno/​binutils-mist32|binutils(assembler,​ linker, etc...) for MIST32 architecture]] ([[https://​github.com/​techno|hktechno]] coded)     * [[https://​github.com/​techno/​binutils-mist32|binutils(assembler,​ linker, etc...) for MIST32 architecture]] ([[https://​github.com/​techno|hktechno]] coded)