Takahiro Ito @cpu_labs

I was a researcher at High Performance Computing System labs. Department of Computer Science, Graduate School of SIE, University of Tsukuba, Japan until August 2016.

Currently, I'm a master's student at College of Electrical Engineering and Computer Science, National Tsing Hua University, Taiwan.

My research aspect are Micro Architecture / Verilog HDL / System Verilog Assertion / VHDL / Hardware Verification / FPGA / Electronic circuit.

I received a Super Creator from the Japanese government in 2011. : What is Super Creator? or see this page.

Ongoing project

  • Open Design Computer Project - This Project is about the creating a new 32-bit processor architecture “MIST32”. The MIST32 processor is instruction sets has been optimized for Out-of-Order execution.



Past research / Presentations

  • [Research of CPU]2009/11/6~2010/3/31 “H21年度先導的研究者体験プログラム データ駆動型プロセッサにおける低消費電力動作性能の評価” University of Tsukuba/Ministry of Education, Culture, Sports, Science and Technology, Japan
  • [Research of CPU]2012/3/1~2012/8/31 “未踏IT 人材発掘育成事業 - Open Design Computer Project” Information-technology Promotion Agency, Japan
  • [Research of high speed calculation accelerator]2014/4/1~2016/8/31 大規模蜜結合型数値演算アクセラレータの研究
  • [Research of CPU]2015/8/11~2015/8/15 National convention of Security Camp 2015 - Teacher
  • [Research of high speed calculation accelerator]伊藤剛浩,山口佳樹,児玉祐悦,山本淳二,中川八穂子,朴泰祐,佐藤三久,“A Study of an ExtremeSIMD Architecture Implemented by an FPGA”, 電子情報通信学会2015年総合大会講演論文集, (D-6-9) pp.73, 草津, 2015年3月.
  • [Research of high speed calculation accelerator]伊藤剛浩, 山口佳樹, 朴泰祐, 佐藤三久, 児玉祐悦, 李珍泌, 山本淳二, 中川八穂子, “A large-scale SIMD architecture : preliminary performance estimation by an FPGA”, 信学技報, Vol.116, No.53, pp.55-60, 川崎, 2016年5月.

Research presentations


Published book

Books(A book my research is being introduced)